FPGA driven Memory Access Tests
Wednesday, 14 July 2010 04:51
Heiko Ehrenberg
Complex FPGA devices typically provide banks of I/O pins that can be configured for a certain logic family (voltage levels and other I/O parameters are programmable/configurable per I/O banks). Typically such devices has reference voltage pins per I/O bank. When the FPGA is not configured, the I/O banks default to a preset logic family, e.g. LVTTL.
Last Updated ( Wednesday, 14 July 2010 04:58 )
Read more...
|
IEEE 1149.4 Summary
Friday, 08 August 2008 02:15
Heiko Ehrenberg
Analog or Mixed signal circuitry is left out by IEEE 1149.1. Recognizing this shortcoming, an IEEE working group was formed in the early 1990s with the purpose to develop a standardized test access methodology for analog and mixed signal pins. In 1999 the effort resulted in the approval of the IEEE Std. 1149.4 (Standard for a Mixed Signal Test Bus). The purpose of this standard is to provide the means to measure and characterize device level or board level mixed-signal and analogue parameters.
Last Updated ( Saturday, 16 August 2008 00:45 )
Read more...
New Boundary Scan I/O Modules enable structural Test of PCI Express Slots via IEEE Std. 1149.6
Monday, 16 June 2008 01:09
Heiko Ehrenberg
During National Electronics Week (NEW), GOEPEL electronic, world-class vendor of JTAG/Boundary Scan solutions compliant with IEEE Std 1149.x, introduced CION Module™ /PCIe-x(1/4) as additional interface cards within the popular CION Module product range.
Read more...
|
IEEE 1149.1 Introduction
Friday, 08 August 2008 02:13
Heiko Ehrenberg
The effort to develop a standardized test method that can solve test access problems caused by ever denser printed circuit designs, shrinking device geometries and new device packaging (such as BGA and CSP) started in the mid 1980s, when a group of European companies and institutions formed the Joint European Test Action Group (JETAG), which later changed its name to Joint Test Action Group (JTAG) when North American organizations joined the group.
Last Updated ( Sunday, 24 August 2008 22:58 )
Read more...
One chain. Or two? Or more?
Sunday, 03 August 2008 03:43
Heiko Ehrenberg
Often times it is recommended to combine all devices on a board to one Boundary Scan chain. However, there are applications where it is beneficial, if not even required, to split up the devices into two or more chains.
Read more...
|
|
|
|
|
|
Page 1 of 2 |
