DFT Guidelines for JTAG/Boundary Scan

Assemble a team of beneficiaries to discuss implementation of Boundary Scan at the design stage (beneficiaries include design engineers, production test engineers, field service engineers). Don’t forget to involve management and procurement to evaluate monetary savings throughout the product life cycle.
All digital I/O pins should have Boundary Scan cells.
Upon power-up and test-logic reset all I/O’s should be set as inputs or Tri-State.
In case of time critical clock pins, capture only cells should be assigned.
Make sure device internal functions can accept any value from BScan cells during test mode without getting damaged.
TDO must go tri-state if the device is not in scan mode.
Never mix core clock with TCK, or core Reset with /TRST, respectively.
Consider putting test bus pins (TCK, TMS, TDI, TDO, /TRST) next to supply (VCC) pins, so that in case of a short, they behave deterministic and no damage to the device can occur.
If compliance pin(s) are used to enable Boundary Scan testability on a component, make sure, only a static value (not a sequential enable pattern) is needed to enable IEEE-1149.1 compliance.
If the Instruction Register is longer than 2 bits, consider using some bits to capture special information such as GO/NOGO result from BIST or device specific data. Bits 1 and 0 of IR have to provide capture code “01”.
To avoid Ground Bounce problems internal delay groups with 100-150 outputs should be designed in.
Allow simultaneous driving/sensing on bi-directional pins (e.g. use BC_7).
Provide individual control cells for Tristate- and Bi-Directional pins, whenever possible. This will increase board-level testability.
A read-back cell should be used for dedicated outputs. This cell reads back the driven value during capture state (result: better diagnosis for opens and sa0/1 faults, respectively).
“Unstress” cells on the outputs can minimize the over-current in case of external stuck at faults. “Unstress” means the driven level is measured back and the drive value is automatically changed to the opposite level in case of a fault (“unstress”) state.
Make sure BSDL files are available from the device vendor and that the files are verified.
All non-compliant features or any requirements to bring the device into IEEE-1149.1 compliant mode shall be documented (preferably in both the BSDL file and the component data sheet).
When the device features mixed-signal or analog kernels and/or I/O’s, consider the implementation of IEEE 1149.4 test features.
When the device features differential and/or high-speed I/O’s, consider the implementation of IEEE 1149.6 test features.

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