A Unit Under Test always includes some integrated and discrete devices that do not provide any IEEE 1149.1 features (we call those "non-BScan" or "non-scanable" devices). Often times such non-BScan devices can be included in Boundary Scan tests if a few simple DFT guidelines are followed.
- Clusters containing non-scanable devices should be minimized to single IC or to combinatorial logic only (if possible).
- Non-scanable devices (buffers, multiplexes, glue logic, memory devices, etc.) should be controllable via Boundary Scan (control nets should contain BScan cells). The same is true for clock signals for synchronous memory banks (clock should be controllable via BScan), etc.
- Providing complete Boundary Scan access to Memory devices allows memory cluster testing, thus increasing test coverage by exercising the memory pins and possibly Boundary Scan pins otherwise not testable.
- Providing complete Boundary Scan access to EEPROM (e.g. FLASH) components allows In-System Programming of such components via Boundary Scan. Programming speed can be increased when control signals such as /WE can be accessed (via connector pin) with parallel I/O resources independent from BScan I/O’s. To utilize such parallel I/O’s the Boundary Scan pin normally controlling the signal needs to be put in Tri-State.
- For memory cluster testing and In-System Programming (e.g. of FLASH devices) a short scan chain is of the essence to keep test time short. Try to connect all memory pins to one Boundary Scan component, so that other devices can be kept in HIGHZ, CLAMP, or BYPASS, while this one component applies the test/programming pattern.
