DFT Guidelines Board Level DFT
FPGA driven Memory Access Tests
Complex FPGA devices typically provide banks of I/O pins that can be configured for a certain logic family (voltage levels and other I/O parameters are programmable/configurable per I/O banks). Typically such devices has reference voltage pins per I/O bank. When the FPGA is not configured, the I/O banks default to a preset logic family, e.g. LVTTL.
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