Although this seems rather obvious, I would like to use this first blog entry to stress the point that JTAG/Boundary Scan only works if the respective test bus signals are accessible. Test bus pins (often called JTAG pins) on an IEEE 1149.1 compliant device make up the Test Access Port (TAP) and include the four mandatory signals TCK, TMS, TDI, and TDO. Some devices feature an optional fifth pin, the low-active /TRST.
- TCK: Test Clock, scan chain and TAP Controller synchronization;
- TMS: Test Mode Select, controlling the TAP Controller State Machine;
- TDI: Test Data In, input signal for instructions and test data;
- TDO: Test Data Out, output signal for response data and data passing through to downstream devices;
- /TRST: Test Logic Reset, asynchronous reset of the TAP Controller State Machine and any IEEE 1149.x test logic;
On a printed circuit board (PCB, also referred to as board throughout this blog), the test bus pins of the IEEE 1149.1 compliant devices are connected together to create a JTAG/Boundary Scan chain. The most typical configuration is the single daisy-chain with the following layout:
- all TCK pins are connected to one TCK signal on the board,
- all TMS pins are connected to one TMS signal on the board,
- the TDI of one device is connected to the TDO of the Boundary Scan controller (the test system hardware driving the test bus), and the TDO of the same device is connected to the TDI of the next device in the chain,
- TDO of one device is connected to TDI of the next device in the chain,
- TDO of the “last” device in the chain is connected to TDO of the Boundary Scan controller, and
- if implemented, the /TRST signal is connected in parallel to all devices featuring this type of test bus pin;
Some boards implement multiple JTAG/Boundary Scan chains and even special JTAG/Boundary Scan chain management/router devices.
