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Home DFT Guidelines Board Level DFT Compliance Enable and Mode Control pins
Board and Module Level DFT Guidelines

Compliance Enable and Mode Control pins

Sunday, 24 August 2008 21:58
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Some IEEE 1149.x compliant devices have so-called Compliance Enable pins, used to enable IEEE 1149.x compliant device features. It is very important to properly accommodate such pins on the board design to ensure that Boundary Scan applications are not obstructed.
 
  • Configuration lines for FPGA should be controllable through BScan (some FPGA don’t allow full BScan testing while they are in configuration mode).
  • Compliance pins should be accessible from the outside of the board via connector pins, or should be set on board (via pull resistors), to permanently allow Boundary Scan access.
  • To disable the TAP during normal board/system function, do not tie compliance pins to Ground or VCC without pull resistors and a connector pin or test pad, otherwise the device can never be brought into test mode.
 

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