The layout of the JTAG test bus signal traces on the printed circuit board (PCB) is very important to ensure good signal quality. Especially the TCK signal needs to be as free as possible of glitches and spikes, since all test access port (TAP) operations are triggered by rising and falling TCK edges.
Routing of Test Bus Signals
- Connection of TDO of last device in scan chain to board TDO should be as short as possible.
- TMS and TCK are broadcast lines. They should be routed in accordance to high-frequency bus rules. In case you have many BScan devices on board, use buffer at board test bus connector to avoid overload of TMS and TCK signals coming from BScan controller.
- Define a unified test bus connector for all (current and future) BScan designs. For example use a 10 pin connector with the following pinout:
Pin #: Signal name 1: TCK 3: TMS 5: TDO (TDI of BScan controller) 7: TDI (TDO of BScan controller) 9: /TRST 2,4,6,8: GND 10: not used
Placement of Signal Terminations
- When using a buffer to distribute TCK, TMS and /TRST on the UUT, put the termination resistors on the primary side (signals coming from BScan controller) of the buffer.
- A serial resistor on the TDO of the last device in the chain should be close to that devices TDO pin.
Placement of Testpoints, Jumpers, Connectors
- In case you are going to use bed of nail testing, assign a test pad for each non-scanable net and each only partially testable net for nail access.
- If the UUT is also connected via the native edge connectors, nails for connector nets can be avoided. (For example, GOEPEL’s BScan I/O modules provide BScan access for edge connectors and/or testpoints.)
- Test bus signals TCK, TMS, /TRST, TDI and TDO should have test pads for fine diagnosis by a probe in case of shorts to other nets or to find opens.
- Connectors for mezzanine module should be easily reachable for test access.
- If many serial resistors are used on the board, some of them should be accessible by test pads for checking of parametric correctness.
