DFT Guide

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DFT Guidelines for Semiconductor Devices

General DFT considerations

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  • Assemble a team of beneficiaries to discuss implementation of Boundary Scan at the design stage (beneficiaries include design engineers, production test engineers, field service engineers). Don’t forget to involve management and procurement to evaluate monetary savings throughout the product life cycle.
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Custom implementations and special features

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To accelerate FLASH programming procedures or other memory operations by Boundary Scan, the pulse generation for respective control signals could be generated internally in conjunction with BST (Boundary Scan Test) logic and/or outputs could be tri-state to apply control lines externally. Consider implementing special registers (including only the cells needed for a specific test application) in ASIC’s, so that scan cells not needed don’t lengthen the scan chain without providing any value for the test.
 

Optional features of IEEE 1149.1 compliant devices

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In addition to mandatory features, the IEEE Std. 1149.1 also specifies optional capabilities and resources. 
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Mandatory features of IEEE 1149.1 compliant devices

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The IEEE Std. 1149.1 specifies both mandatory and optional device features. Mandatory features include the following:

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Free tool for BSDL syntax verification

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GOEPEL offers a free tool that allows users to verify BSDL files compliant to IEEE 1149.1, IEEE 1149.6 , and IEEE 1532 standards. As soon as the “Analog BSDL” for IEEE 1149.4 compliant devices is standardized, the BSDL SyntaxChecker will officially support that dialect as well. This software tool is called BSDL Syntax Checker and is available on the download page.

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Jena, Germany; Las Vegas, NV – At the APEX tradeshow, GÖPEL electronic, a worldwide leading vendor of JTAG/Boundary Scan solutions compliant to IEEE1149.x, introduces a brand-new I/O module called CION Module™/FXT114S. 
 
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